A flash memory device generally includes an array of memory cells arranged in rows and columns. Each memory cell includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. The gate corresponds to a word line, and the drain or source correspond to bit lines of the memory array.
The semiconductor industry is increasingly driven towards smaller and more capable electronic devices, such as computing devices, communication devices, and memory devices. In order to increase the capacity of the devices, three-dimensional (“3D”) or vertical memory cell arrays have been formed comprising multiple vertical layers of gates along a substrate.
Applicant has identified deficiencies and problems associated with conventional processes for manufacturing vertical memory cells and the resulting memory devices. Through applied effort, ingenuity, and innovation, certain of these identified problems have been solved by developing solutions that are included in various embodiments of the present invention, which are described in detail below.